1. Field of the Invention
The present invention pertains in general to a frequency conversion device, and more particularly, a single-ended upconverter.
2. Description of the Related Art
U.S. Pat. No. 5,625,307, to Scheinberg entitled, “Low Cost Monolithic GaAs Upconverter Chip” (“Scheinberg”) describes an improvement upon a known frequency upconverter employing a Gilbert type double-balanced mixer. Scheinberg is hereby incorporated by reference.
A frequency upconverter generally includes an RF amplifier to amplify a radio frequency (“RF”) input signal, a local oscillator (“LO”) to generate a LO signal, and a mixer to combine the RF input and LO signals to generate an intermediate frequency (“IF”) signal. FIG. 1 is a general block diagram of a known upconverter for double-conversion 102. Referring to FIG. 1, upconverter 102 includes a low-noise amplifier (“LNA”) 104, a Gilbert type image-rejecting mixer 106, a phase splitter 110, a voltage-controlled oscillator (“VCO”) 112 and a DC bias circuit 108. Upconverter 102 also includes sixteen pins, #1 to #16. Pin #6 receives an input signal RF and couples input signal RF to LNA 104, which, in turn, provides a differential output signal to mixer 106 to generate differential IF signals at ports #1 and #16. Differential IF signals have frequencies higher than that of the input RF signal.
FIG. 2 is a functional block diagram of LNA 104 and mixer 106 of FIG. 1. Referring to FIG. 2, input signal RF is transformed into a differential pair, RF+ and RF−, through an external capacitor-inductor-capacitor circuit 114. Differential pair RF+ and RF− may also be created through an alternative embodiment of a Balun circuit 114A. LNA 104 receives differential pair RF+ and RF− as input signals and provide output signals to mixer 106. Mixer 106 additionally receives differential signals LO to generate differential IF signals. Because LNA 104 requires differential-pair RF input signals, an external circuit, one such as Balun circuit 114, is always required. Such an external circuit is disadvantageous because it occupies additional chip area on a semiconductor wafer. FIG. 3 shows a schematic diagram of FIG. 2 as described in Scheinberg.
FIG. 4 is a functional block diagram of a conventional differential-pair input upconverter employing RF bypass networks. Referring to FIG. 4, an RF bypass network 116 is disposed between the input terminals of LNA 104 and differential-pair signals RF+ and RF−. RF bypass network 116 includes a first resistor 118, a second resistor 120, and a capacitor 122 connected in series. One end of capacitor 122 is coupled to resistor 120 and the other end of capacitor 122 is coupled to ground. RF bypass network 116 functions to dampen potential resonances of upconverter 102 created by bond wires (not shown) or the parasitic self-inductances of the package pins (not shown). However, RF bypass network 116 lacks preferred resistance matching at the input end of upconverter 102 and control of high-frequency image signals. FIG. 5 is a schematic diagram of FIG. 4.
FIG. 6 is a schematic diagram of a conventional differential-pair input upconverter including source degeneration networks. Referring to FIG. 6, LNA of upconverter 102 includes a first transistor 138, a second transistor 140, and a source degeneration network 124. Source degeneration network 124 includes matched source-degenerating inductors 126 and 128 and resistors 142 and 144 to eliminate noise created by transistors 138 and 140 and control image noise. Another embodiment of a source degeneration network is shown as 124A, including only source degenerating inductors. Although source degeneration resistors 142 and 144 improve the linearity of transistors 138 and 140 of LNA 104, source degeneration resistors 142 and 144 also decrease the gain of LNA 104. Similarly, although source degeneration inductors 126 and 128 inhibit image noise, inductors 126 and 128 do not provide for the linearity, conversion gain, or noise figure characteristics of LNA 104 or mixer 106.
Scheinberg additionally describes a DC bias circuit to address long power-up latencies in the order of several seconds, which cause an increased testing time. FIG. 7 is a schematic diagram of Scheinberg including a DC bias circuit that includes resistors 130, 132, and 134. A passive voltage-dividing network is shown in FIG. 7. The gate of transistor 136, which functions as a current source, is biased by the voltage-dividing network comprising resistor 130, 132, and 134, which act to prevent power-up latency. However, this design complicates the overall circuit design of upconverter 102.
Furthermore, when a upconverter chip is packaged, an external resonator is coupled to an internal VCO. The external resonator is grounded directly to an internal ground node of the upconverter chip or a ground node of the Printed Circuit Board (PCB). As a result, noise generated by the external resonator may be coupled to the internal VCO or other internal components of the upconverter through the common ground connection.